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IEICE Trans

Keyword : parallel communication

Parallel VLSI Processors for Robotics Using Multiple Bus Interconnection Networks
Bumchul KIM Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/06/25
Vol. E75-A  No. 6 ; pp. 712-719
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1991 Joint Technical Conference on Circuits/Systems, Computers and Communications (JTC-CSCC '91))
Category: Robot Electronics
Keyword: 
minimum-delay-time architecture, VLSI processor for robotics, parallel processing, parallel communication, multiple bus interconnection networks, 
 Summary | Full Text:PDF