Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A
No. 12 ;
pp. 3602-3612
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Architecture
Keyword:
low-density parity-check codes, parallel LDPC decoder architecture, message-passing algorithm, FIFO-based buffering, |