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IEICE Trans

Keyword : multiple clock operation

Timing Verification of Sequential Logic Circuits Based on Controlled Multi-Clock Path Analysis
Kazuhiro NAKAMURA Shinji KIMURA Kazuyoshi TAKAGI Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A  No. 12 ; pp. 2515-2520
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Timing Verification and Optimization
Keyword: 
timing verification, maximum delay analysis, multiple clock operation, false path, 
 Summary | Full Text:PDF