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IEICE Trans

Keyword : multiple cell upset (MCU)

Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
Shusuke YOSHIMOTO Shunsuke OKUMURA Koji NII Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7 ; pp. 1579-1585
Type of Manuscript:  PAPER
Category: Reliability, Maintainability and Safety Analysis
Keyword: 
SRAM, soft error rate (SER), multiple cell upset (MCU), neutron particle, twin well, triple well, 
 Summary | Full Text:PDF