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IEICE Trans

Keyword : majority logic decoding

A 50 MHz CMOS Pipelined Majority Logic Decoder for (1057, 813) Difference-Set Cyclic Code
Kazumasa KOBAYASHI Kouji YAMANO Hideki KOKUBUN Kiichi KOBAYASHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1996/07/25
Vol. E79-A  No. 7 ; pp. 1060-1067
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
difference-set cyclic codes, (1057,813) code, majority logic decoding, pipelining, 
 Summary | Full Text:PDF