Design of an Area-Efficient and Low-Power NoC Architecture Using a Hybrid Network Topology Woo Joo KIMSun Young HWANG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2008/11/01 Vol. E91-ANo. 11 ;
pp. 3297-3303 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: network on chip, hybrid network topology, low-power algorithm, job distribution,