|
| Keyword : logic verification
| |
| |
| |
|
Extraction of Behavioral Descriptions from Synchronous Sequential Circuits
Masahiko OHMURA Hiroto YASUURA Keikichi TAMARU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/10/25
Vol. E75-A
No. 10 ;
pp. 1239-1246
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category:
Keyword:
behavioral extraction, logic verification, | | | Summary | Full Text:PDF | |
|
|