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IEICE Trans

Keyword : logic utilization

A New FPGA Architecture for High Performance Bit-Serial Pipeline Datapath
Akihisa OHTA Tsuyoshi ISSHIKI Hiroaki KUNIEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/08/25
Vol. E83-A  No. 8 ; pp. 1663-1672
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
FPGA, bit-serial, logic block architecture, routing architecture, logic utilization, Rent's rule, chip scalability, 
 Summary | Full Text:PDF