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| Keyword : logic optimization
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Reduction of the Number of FPGA Blocks by Maximizing Flexibility of Internal Functions
Takenori KOUDA Shigeru YAMASHITA Yahiko KAMBAYASHI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/12/25
Vol. E81-A
No. 12 ;
pp. 2554-2562
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword:
logic optimization, FPGAs, SPFDs, PSPFDs, | | | Summary | Full Text:PDF | |
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Logic Optimization: Redundancy Addition and Removal Using Implication Relations
Hideyuki ICHIHARA Kozo KINOSHITA | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 1998/07/25
Vol. E81-D
No. 7 ;
pp. 724-730
Type of Manuscript:
Special Section PAPER (Special Issue on Test and Diagnosis of VLSI)
Category: Logic Simulation and Logic Optimization
Keyword:
logic optimization, implication, redundancy identification, | | | Summary | Full Text:PDF | |
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