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IEICE Trans

Keyword : logic debugging

Signal Selection Methods for Debugging Gate-Level Sequential Circuits
Yusuke KIMURA Amir Masoud GHAREHBAGHI Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2019/12/01
Vol. E102-A  No. 12 ; pp. 1770-1780
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
logic debugging, engineering change order (ECO), sequential circuits, reachability analysis, 
 Summary | Full Text:PDF