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IEICE Trans

Keyword : leveling

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1733-1738
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
low-power, leveling, dynamic logic, over-lapped clock, power control, 
 Summary | Full Text:PDF
Initial Leveling of Strapdown Inertial Navigation System with an On-Line Robust Input Estimator
Sou-Chen LEE Cheng-Yu LIU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/11/25
Vol. E81-A  No. 11 ; pp. 2383-2390
Type of Manuscript:  PAPER
Category: Digital Signal Processing
Keyword: 
strapdown inertial navigation system, leveling, generalized M estimator, input estimation, 
 Summary | Full Text:PDF