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IEICE Trans

Keyword : layout-area allocation

Wire Length Distribution Model for System LSI
Takanori KYOGOKU Junpei INOUE Hidenari NAKASHIMA Takumi UEZONO Kenichi OKADA Kazuya MASU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/12/01
Vol. E88-A  No. 12 ; pp. 3445-3452
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Interconnect
Keyword: 
wire length distribution, core utilization, SoC, layout-area allocation, 
 Summary | Full Text:PDF