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IEICE Trans

Keyword : layer assignment

Temperature-Aware Layer Assignment for Three-Dimensional Integrated Circuits
Shih-Hsu HUANG Hua-Hsin YEH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/08/01
Vol. E97-A  No. 8 ; pp. 1699-1708
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
electronic design automation, high-level design stage, design partitioning, layer assignment, three-dimensional integrated circuits, temperature increase, 
 Summary | Full Text:PDF
Crosstalk and Congestion Driven Layer Assignment Algorithm
Bin LIU Yici CAI Qiang ZHOU Xianlong HONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/06/01
Vol. E88-A  No. 6 ; pp. 1565-1572
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
congestion, crosstalk, layer assignment, VLSI, 
 Summary | Full Text:PDF
A Multi-Layer Channel Router Using Simulated Annealing
Masahiko TOYONAGA Chie IWASAKI Yoshiaki SAWADA Toshiro AKINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2085-2091
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
channel router, simulated annealing, layer assignment, compaction, 
 Summary | Full Text:PDF
Testing the k-Layer Routability in a Circular Channel--Case in which No Nets Have Two Terminals on the Same Circle--
Noriya KOBAYASHI Toshinobu KASHIWABARA Sumio MASUDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1992/02/25
Vol. E75-A  No. 2 ; pp. 233-239
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
algorithm, routing, via minimization, layer assignment, 
 Summary | Full Text:PDF