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IEICE Trans

Keyword : intermediate message compression technique

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique
Kazunori SHIMIZU Nozomu TOGAWA Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1054-1061
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
low-density parity-check code, message-passing algorithm, intermediate message compression technique, clock gated shift register for intermediate message, 
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