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IEICE Trans

Keyword : interconnection nodes

A Circuit Partitioning Approach for Parallel Circuit Simulation
Tetsuro KAGE Fumiyo KAWAFUJI Junichi NIITSUMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/03/25
Vol. E77-A  No. 3 ; pp. 461-466
Type of Manuscript:  Special Section PAPER (Special Section on the 6th Karuizawa Workshop on Circuits and Systems)
Category: Modeling and Simulation
Keyword: 
circuit partitioning, parallel circuit simulation, subcircuits, interconnection nodes, bordered-block-diagonal (BBD) matrix, 
 Summary | Full Text:PDF