Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/12/01
Vol. E96-A
No. 12 ;
pp. 2467-2474
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Level Design
Keyword:
crosstalk, delay effects, insertion buffer, interconnect-driven floorplanning, noise-aware buffer planning, |