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IEICE Trans

Keyword : interconnect fault tolerance

Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip
Katherine Shu-Min LI Chih-Yun PAI Liang-Bi CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/12/01
Vol. E94-A  No. 12 ; pp. 2649-2658
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword: 
interconnect fault tolerance, interconnect testing, interconnect diagnosis, interconnect resilience, oscillation ring scheme, 
 Summary | Full Text:PDF