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IEICE Trans

Keyword : input reordering

A Power and Delay Optimization Method Using Input Reordering in Cell-Based CMOS Circuits
Masanori HASHIMOTO Hidetoshi ONODERA Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/01/25
Vol. E82-A  No. 1 ; pp. 159-166
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
input reordering, transistor reordering, power estimation, 
 Summary | Full Text:PDF