Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2022/03/01 Vol. E105-ANo. 3 ;
pp. 459-467 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: convex hull, hardware algorithm, FPGA, approximated algorithm,
High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation Masamitsu TANAKAKazuyoshi TAKAGINaofumi TAKAGI
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2010/04/01 Vol. E93-CNo. 4 ;
pp. 429-434 Type of Manuscript: INVITED PAPER (Special Section on Frontiers of Superconductive Electronics) Category: Keyword: single-flux-quantum (SFQ) circuit, adder, hardware algorithm,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/05/01 Vol. E85-ANo. 5 ;
pp. 994-999 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: finite field arithmetic, division in finite field, hardware algorithm, VLSI algorithm,
A Digit-Recurrence Algorithm for Cube Rooting Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/05/01 Vol. E84-ANo. 5 ;
pp. 1309-1314 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: computer arithmetic, cube rooting, hardware algorithm, digit-recurrence algorithm, VLSI,
A Novel Computationally Adaptive Hardware Algorithm for Video Motion Estimation Vasily G. MOSHNYAGA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 1999/09/25 Vol. E82-CNo. 9 ;
pp. 1749-1754 Type of Manuscript: Special Section PAPER (Special Issue on Integrated Electronics and New System Paradigms) Category: Imaging Circuits and Algorithms Keyword: video processing, motion estimation, hardware algorithm, VLSI architecture,
A VLSI Algorithm for Modular Division Based on the Binary GCD Algorithm Naofumi TAKAGI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/05/25 Vol. E81-ANo. 5 ;
pp. 724-728 Type of Manuscript: Special Section PAPER (Special Section on Discrete Mathematics and Its Applications) Category: Keyword: modular arithmetic, modular division, GCD, hardware algorithm, redundant representation,