Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/12/01 Vol. E101-ANo. 12 ;
pp. 2308-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, steady state, signal transition, logic test,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-ANo. 12 ;
pp. 2335-2347 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, a quantitative criterion, pattern matching, design phase,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-ANo. 12 ;
pp. 2537-2546 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: hardware Trojans, golden-IC free, classification, identification, gate-level netlist,