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IEICE Trans

Keyword : gated-clock

Bipartition and Synthesis in Low Power Pipelined Circuits
Shyh-Jong CHEN Rung-Ji SHANG Xian-June HUANG Shang-Jang RUAN Feipei LAI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/04/25
Vol. E81-A  No. 4 ; pp. 664-671
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
bipartition, synthesis, low power, gated-clock, pipelined circuit, 
 Summary | Full Text:PDF