Hardware-Trojan Detection Based on the Structural Features of Trojan Circuits Using Random Forests Tatsuki KURIHARANozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2022/07/01 Vol. E105-ANo. 7 ;
pp. 1049-1060 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: hardware Trojan, trigger circuit, gate-level netlist, machine learning, random forest,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2021/11/01 Vol. E104-ANo. 11 ;
pp. 1516-1525 Type of Manuscript: Special Section PAPER (Special Section on Circuits and Systems) Category: Keyword: hardware Trojan, gate-level netlist, design time, neural networks, machine learning,
Publication: IEICE TRANSACTIONS on Information and Systems Publication Date: 2020/07/01 Vol. E103-DNo. 7 ;
pp. 1618-1622 Type of Manuscript: Special Section LETTER (Special Section on Information and Communication System Security) Category: Network and System Security Keyword: hardware Trojan, gate-level netlist, Trojan feature, boundary nets, hardware design,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/12/01 Vol. E101-ANo. 12 ;
pp. 2308-2319 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, steady state, signal transition, logic test,
Empirical Evaluation and Optimization of Hardware-Trojan Classification for Gate-Level Netlists Based on Multi-Layer Neural Networks Kento HASEGAWAMasao YANAGISAWANozomu TOGAWA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2018/12/01 Vol. E101-ANo. 12 ;
pp. 2320-2326 Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, detection, gate-level netlist, multi-layer neural networks, machine learning,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2017/12/01 Vol. E100-ANo. 12 ;
pp. 2857-2868 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojan, gate-level netlist, Trojan-net feature, random forest, machine learning,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2017/07/01 Vol. E100-ANo. 7 ;
pp. 1427-1438 Type of Manuscript: Special Section PAPER (Special Section on Design Methodologies for System on a Chip) Category: Keyword: hardware Trojan, gate-level netlist, machine learning, support vector machine (SVM), neural network (NN),
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2016/12/01 Vol. E99-ANo. 12 ;
pp. 2335-2347 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Keyword: hardware Trojans, gate-level netlist, a quantitative criterion, pattern matching, design phase,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2015/12/01 Vol. E98-ANo. 12 ;
pp. 2537-2546 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis, Test and Verification Keyword: hardware Trojans, golden-IC free, classification, identification, gate-level netlist,