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IEICE Trans

Keyword : fully concurrent operation

The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
Yun YANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/04/01
Vol. E91-A  No. 4 ; pp. 1101-1111
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
jumping systolic array (JSA), processing element (PE), matrix multiplication, fully concurrent operation, fast process speed, 
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