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IEICE Trans

Keyword : fractional phase-locked loop

A 3.2-GHz Down-Spread Spectrum Clock Generator Using a Nested Fractional Topology
Ching-Yuan YANG Chih-Hsiang CHANG Wen-Ger WONG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2008/02/01
Vol. E91-A  No. 2 ; pp. 497-503
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
spread spectrum clock generation, fractional phase-locked loop, delay-locked loop, phase compensation, fractional divider, 
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