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IEICE Trans

Keyword : finite state machine with datapath

Multi-Level Bounded Model Checking with Symbolic Counterexamples
Tasuku NISHIHARA Takeshi MATSUMOTO Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A  No. 2 ; pp. 696-705
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
formal verification, bounded model checking, finite state machine with datapath, symbolic simulation, 
 Summary | Full Text:PDF