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IEICE Trans

Keyword : finite input-memory automaton

Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping
Chengjie ZANG Shinji KIMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/06/01
Vol. E92-A  No. 6 ; pp. 1454-1463
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
SystemVerilog Assertion, assertion checker, finite input-memory automaton, 
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