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A Novel Parallel 8B/10B Encoder: Architecture and Comparison with Classical Solution
Pietro NANNIPIERI Daniele DAVALLE Luca FANUCCI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/07/01
Vol. E101-A
No. 7 ;
pp. 1120-1122
Type of Manuscript:
LETTER
Category: Digital Signal Processing
Keyword:
VLSI, 8b10b, parallel, encoding, | | | Summary | Full Text:PDF | |
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Two-Way Parity Bit Correction Encoding Algorithm for Dual-Diagonal LDPC Codes
Chia-Yu LIN Chih-Chun WEI Mong-Kai KU | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/02/01
Vol. E94-A
No. 2 ;
pp. 773-780
Type of Manuscript:
PAPER
Category: Coding Theory
Keyword:
LDPC codes, dual-diagonal codes, encoding, | | | Summary | Full Text:PDF | |
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Instruction Encoding for Reducing Power Consumption of I-ROMs Based on Execution Locality
Koji INOUE Vasily G. MOSHNYAGA Kazuaki MURAKAMI | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/04/01
Vol. E86-A
No. 4 ;
pp. 799-805
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 15th Workshop on Circuits and Systems in Karuizawa)
Category:
Keyword:
low power, instruction ROM, embedded systems, encoding, | | | Summary | Full Text:PDF | |
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Addition of Integers in a Computer Memory: Information Theory Approach
Vladimir B. BALAKIRSKY | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/10/25
Vol. E83-A
No. 10 ;
pp. 1929-1935
Type of Manuscript:
Special Section PAPER (Special Section on Information Theory and Its Applications)
Category: Code for Computer Memory
Keyword:
encoding, decoding, multi-user communication, addition, parallel processing, | | | Summary | Full Text:PDF | |
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