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IEICE Trans

Keyword : dynamic logic

Reconfigurable Dynamic Logic Circuit Generating t-Term Boolean Functions Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Yasuyuki MIURA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/05/01
Vol. E97-A  No. 5 ; pp. 1051-1058
Type of Manuscript:  PAPER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs, 
 Summary | Full Text:PDF
Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs
Manabu KOBAYASHI Hiroshi NINOMIYA Shigeyoshi WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2013/07/01
Vol. E96-A  No. 7 ; pp. 1642-1644
Type of Manuscript:  LETTER
Category: Circuit Theory
Keyword: 
reconfigurable logic circuit, ambipolar double-gate devices, dynamic logic, CNTFETs, 
 Summary | Full Text:PDF
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment
Benjamin STEFAN DEVLIN Toru NAKURA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/07/01
Vol. E93-A  No. 7 ; pp. 1319-1328
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
self synchronous, fpga, pipeline alignment, low power, high throughput, dynamic logic, dual pipeline, 
 Summary | Full Text:PDF
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic
Akira MOCHIZUKI Hirokatsu SHIRAHAMA Takahiro HANYU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1591-1597
Type of Manuscript:  Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
differential-pair circuit, current-mode circuit, multiple-valued logic, dynamic logic, 
 Summary | Full Text:PDF
A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
Hiroyuki MATSUBARA Takahiro WATANABE Tadao NAKAMURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/11/25
Vol. E83-C  No. 11 ; pp. 1733-1738
Type of Manuscript:  Special Section PAPER (Special Issue on Low-power LSIs and Technologies)
Category: 
Keyword: 
low-power, leveling, dynamic logic, over-lapped clock, power control, 
 Summary | Full Text:PDF