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IEICE Trans

Keyword : dual-looped PLL

A 3.3 V CMOS Dual-Looped PLL with a Current-Pumping Algorithm
Hyuk-Jun SUNG Kwang Sub YOON 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/02/25
Vol. E83-A  No. 2 ; pp. 267-271
Type of Manuscript:  Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
dual-looped PLL, PFD, VCO, V-I converter, current-pumping algorithm, 
 Summary | Full Text:PDF