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IEICE Trans

Keyword : design methodology for security hardware

Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors
Rei UENO Naofumi HOMMA Takafumi AOKI Sumio MORIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2017/07/01
Vol. E100-A  No. 7 ; pp. 1396-1408
Type of Manuscript:  Special Section PAPER (Special Section on Design Methodologies for System on a Chip)
Category: 
Keyword: 
design methodology for security hardware, formal design, cryptographic processors, Galois field, arithmetic circuits, 
 Summary | Full Text:PDF