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IEICE Trans

Keyword : dependable architectures

High-Performance Architecture for Concurrent Error Detection for AES Processors
Takeshi SUGAWARA Naofumi HOMMA Takafumi AOKI Akashi SATOH 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/10/01
Vol. E94-A  No. 10 ; pp. 1971-1980
Type of Manuscript:  PAPER
Category: Cryptography and Information Security
Keyword: 
dependable architectures, fault injection attacks, tamper resistance, error detection, 
 Summary | Full Text:PDF