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IEICE Trans

Keyword : computation-in-memory

ReRAM Resistance Design of LRS and HRS for Ultrahigh-Capacity Digital Memory and Analog Computation-in-Memory
Chihiro MATSUI Ayumu YAMADA Naoko MISAWA Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3 ; pp. 596-603
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
computation-in-memory, digital memory, current-sensing, interconnection resistance, 
 Summary | Full Text:PDF
RGB-Event Multi-Modal NV-CiM to Detect Object by Mapping-Oriented Enhanced-Feature Pyramid Network with Mapping-Aware Group Convolution
Yuya ICHIKAWA Naoko MISAWA Chihiro MATSUI Ken TAKEUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/03/01
Vol. E108-A  No. 3 ; pp. 482-490
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
computation-in-memory, group convolution, subarray separation, multi-modal AI, non-volatile memory, 
 Summary | Full Text:PDF