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IEICE Trans

Keyword : centralized shared buffer

Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks
Po-Tsang HUANG Wei HWANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2011/11/01
Vol. E94-A  No. 11 ; pp. 2412-2424
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
two-level FIFO buffer, centralized shared buffer, router, on-chip interconnection network, 
 Summary | Full Text:PDF