Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2013/06/01 Vol. E96-ANo. 6 ;
pp. 1283-1292 Type of Manuscript: Special Section PAPER (Special Section on Circuit, System, and Computer Technologies) Category: Keyword: cache simulation, optimaize cache memory, multicore cache,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/12/01 Vol. E92-ANo. 12 ;
pp. 3238-3247 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Embedded, Real-Time and Reconfigurable Systems Keyword: two-level cache, L1/L2, cache optimization, design space exploration, cache simulation, embedded system,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2009/06/01 Vol. E92-ANo. 6 ;
pp. 1442-1453 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: cache, cache optimization, design space exploration, cache simulation, embedded system,