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IEICE Trans

Keyword : bus-based architecture

A Hierarchical Cost Estimation Technique for High Level Synthesis
Mahmoud MERIBOUT Masato MOTOMURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/02/01
Vol. E86-A  No. 2 ; pp. 444-461
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
high level synthesis, hardware cost estimation, multiplexer-based architecture, bus-based architecture, scheduling, allocation, partitioning, 
 Summary | Full Text:PDF