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IEICE Trans

Keyword : bus

Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis
Eui-Young CHUNG Hyuk-Jun LEE Sung Woo CHUNG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/04/01
Vol. E90-A  No. 4 ; pp. 875-878
Type of Manuscript:  LETTER
Category: VLSI Design Technology and CAD
Keyword: 
bus functional model, bus, stochastic, performance, inter-play, 
 Summary | Full Text:PDF
Latency-Aware Bus Arbitration for Real-Time Embedded Systems
Minje JUN Kwanhu BANG Hyuk-Jun LEE Eui-Young CHUNG 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2007/03/01
Vol. E90-D  No. 3 ; pp. 676-679
Type of Manuscript:  LETTER
Category: VLSI Systems
Keyword: 
latency, arbiter, QoS, performance, bus, slack, 
 Summary | Full Text:PDF
Optimal Sorting Algorithms on Bus-Connected Processor Arrays
Koji NAKANO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/11/25
Vol. E76-A  No. 11 ; pp. 2008-2015
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
sorting, parallel algorithm, processor array, bus, 
 Summary | Full Text:PDF