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IEICE Trans

Keyword : bit-parallel cellular array multipliers

Computation of AB2 Multiplier in GF(2m) Using an Efficient Low-Complexity Cellular Architecture
Chung-Hsin LIU Nen-Fu HUANG Chiou-Yng LEE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2000/12/25
Vol. E83-A  No. 12 ; pp. 2657-2663
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
inner product, cyclic shifting, bit-parallel cellular array multipliers, irreducible AOP, canonical basis, 
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