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IEICE Trans

Keyword : bit reusing strategy

A CAM-Based Parallel Fault Simulation Algorithm with Minimal Storage Size
Shinsuke OHNO Masao SATO Tatsuo OHTSUKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1995/12/25
Vol. E78-A  No. 12 ; pp. 1755-1764
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
Content Addressable Memory (CAM), parallel fault simulation, bit reusing strategy, pipeline propagation, hardware engine, 
 Summary | Full Text:PDF