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IEICE Trans

Keyword : bit length

Bit Length Optimization of Fractional Part on Floating to Fixed Point Conversion for High-Level Synthesis
Nobuhiro DOI Takashi HORIYAMA Masaki NAKANISHI Shinji KIMURA Katsumasa WATANABE 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3184-3191
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
HDL, high-level synthesis, parallelizing compiler, bit length, 
 Summary | Full Text:PDF