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IEICE Trans

Keyword : assertion-based verification

Synchronization Verification in System-Level Design with ILP Solvers
Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3387-3396
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
formal verification, SpecC language, event synchronization, Boolean programs, automatic abstraction refinement, assertion-based verification, 
 Summary | Full Text:PDF