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IEICE Trans

Keyword : array multipler

An Architecture for High Speed Array Multiplier
Farhad Fuad ISLAM Keikichi TAMARU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1993/08/25
Vol. E76-A  No. 8 ; pp. 1326-1333
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
binary multiplication, array multipler, VLSI architecture, 
 Summary | Full Text:PDF