Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2002/12/01 Vol. E85-ANo. 12 ;
pp. 2725-2736 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Logic Synthesis Keyword: alternative wire, logic transformation, logic synthesis,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2001/12/01 Vol. E84-ANo. 12 ;
pp. 3116-3124 Type of Manuscript: PAPER Category: VLSI Design Technology and CAD Keyword: logic synthesis, redundant wire, alternative wire, mandatory assignment, layout synthesis,