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IEICE Trans

Keyword : adder tree

Minimum Cut Linear Arrangement of p-q Dags for VLSI Layout of Adder Trees
Kazuyoshi TAKAGI Naofumi TAKAGI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/05/25
Vol. E82-A  No. 5 ; pp. 767-774
Type of Manuscript:  Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
graph algorithm, minimum cut linear arrangement, VLSI layout, adder tree, multiplier, 
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