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IEICE Trans

Keyword : VLSI development cycle

An Analysis of the Economics of the VLSI Development Including Test Cost
Koji NAKAMAE Homare SAKAMOTO Hiromu FUJIOKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/04/25
Vol. E77-A  No. 4 ; pp. 698-705
Type of Manuscript:  PAPER
Category: Computer Aided Design (CAD)
Keyword: 
testing and verification, economics of VLSI development, test cost, VLSI development cycle, EB tester, FIB reconstruction, fault modeling, 
 Summary | Full Text:PDF