SystemVerilog-Based Verification Environment Employing Multiple Inheritance of SystemC Myoung-Keun YOUGi-Yong SONG
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2010/05/01 Vol. E93-ANo. 5 ;
pp. 989-992 Type of Manuscript: LETTER Category: VLSI Design Technology and CAD Keyword: SystemVerilog, SystemC, verification environment, layered-testbench, multiple inheritance,