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IEICE Trans

Keyword : SpecC language

Synchronization Verification in System-Level Design with ILP Solvers
Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/12/01
Vol. E89-A  No. 12 ; pp. 3387-3396
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: System Level Design
Keyword: 
formal verification, SpecC language, event synchronization, Boolean programs, automatic abstraction refinement, assertion-based verification, 
 Summary | Full Text:PDF
Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment
Yu LIU Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2006/04/01
Vol. E89-A  No. 4 ; pp. 1018-1026
Type of Manuscript:  Special Section PAPER (Special Section on Selected Papers from the 18th Workshop on Circuits and Systems in Karuizawa)
Category: 
Keyword: 
AMS extension, system level design language, timed/untimed, mixed-signal, synchronization, SpecC language, 
 Summary | Full Text:PDF
Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams
Thanyapat SAKUNKONCHAK Satoshi KOMATSU Masahiro FUJITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3192-3199
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic and High Level Synthesis
Keyword: 
SpecC language, event synchronization, difference decision diagrams (DDDs), Boolean programs, abstraction refinement, 
 Summary | Full Text:PDF