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IEICE Trans

Keyword : SAT attack

CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level
Masayoshi YOSHIMURA Atsuya TSUJIKAWA Toshinori HOSOKAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/03/01
Vol. E107-A  No. 3 ; pp. 583-591
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Technology and CAD
Keyword: 
logic locking, register transfer level, SAT attack, FALL attack, design for security, controller, 
 Summary | Full Text:PDF
SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking
Yung-Chih CHEN 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2020/05/01
Vol. E103-A  No. 5 ; pp. 733-740
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
logic encryption, IC camouflaging, IC protection, SAT attack, 
 Summary | Full Text:PDF