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IEICE Trans

Keyword : HDL conversion

Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser
Naohiko SHIMIZU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/12/01
Vol. E86-A  No. 12 ; pp. 3225-3229
Type of Manuscript:  Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
Category: Design Methodology
Keyword: 
logic synthesis, HDL conversion, SFL, verilog, 
 Summary | Full Text:PDF