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IEICE Trans

Keyword : FPGA-based acceleration

High-Parallelism and Pipelined Architecture for Accelerating Sort-Merge Join on FPGA
Meiting XUE Wenqi WU Jinfeng LUO Yixuan ZHANG Bei ZHAO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/10/01
Vol. E107-A  No. 10 ; pp. 1582-1594
Type of Manuscript:  PAPER
Category: Algorithms and Data Structures
Keyword: 
FPGA-based acceleration, database, join operation, sort, 
 Summary | Full Text:PDF