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IEICE Trans

Keyword : CMOS logic cell

Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2005/07/01
Vol. E88-A  No. 7 ; pp. 1957-1963
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
comprehensive cell layout synthesis, CMOS logic cell, critical area, defect sensitivity, yield optimization, 
 Summary | Full Text:PDF
High Speed Layout Synthesis for Minimum-Width CMOS Logic Cells via Boolean Satisfiability
Tetsuya IIZUKA Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3293-3300
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
high speed, cell layout synthesis, Boolean Satisfiability, SAT, CMOS logic cell, minimum width, 
 Summary | Full Text:PDF